1. Field of the Invention
This invention relates to integrated circuits and, in particular, to the electrical interconnection of integrated circuit chips to other electronic components and electrically conductive material. Most particularly, the invention relates to the interconnection of an integrated circuit chip and substrate in which electrically conductive traces, vias, and/or regions are formed.
2. Related Art
In current integrated circuit technology, there are three primary methods for routing electrical signals to and from an integrated circuit chip (a semiconductor die in which electrically conductive circuitry is formed) in a packaged integrated circuit. These three methods of chip-level interconnection are wirebonding, tape automated bonding (TAB), and controlled collapse chip connection (C4). Currently, wirebonding is used in approximately 97% of packaged integrated circuits, because wirebonding is inexpensive relative to the other two methods, and because wirebonding machines are programmable, thus enabling many different integrated circuit chip types to be quickly and easily interconnected to a variety of package options.
In wirebonding, one end of an electrically conductive wire (bond wire) is attached to a bond pad (which is electrically connected to the circuitry on the chip) on the integrated circuit chip. The other end of the wire is attached to an off-chip bonding location to which it is desired to make electrical connection such as, for example, an end of an electrically conductive lead or a bonding contact on a substrate. A plurality of bond wires are used in this manner to connect selected bond pads on the chip to selected off-chip bonding locations.
Wirebonding has some disadvantages. Each bond wire adds inductance and capacitance that create noise in the electrical signals traveling to and from the chip through the bond wire. Further, the bond wires typically arc from the bond pads to the off-chip bonding location so that the profile (thickness) of the packaged integrated circuit is thicker than it need necessarily be. Additionally, there is some distance between the chip and the off-chip bonding location over which the bond wires extend so that the density with which chips can be placed on a substrate of, for instance, a multichip module is less than is ideally desirable. Finally, bond wire sweep (i.e., displacement of bond wires that may occur during and as a result of the process for encapsulating the chip) may result in undesirable electrical shorting between adjacent bond wires.
TAB partially overcomes these problems by eliminating bond wires and making direct connection between the bond pads on the chip and the inner end of each of a set of leads that are formed in an electrically insulative tape. Bond wire sweep and undesirably large package profile are no longer problems, but, since leads are still present, electrical noise due to lead inductance and capacitance is still undesirably large and chip density in multichip modules is not as small as possible. Further, TAB is expensive to implement.
The C4 interconnection method overcome the wirebonding problems by eliminating bond wires and leads, thus making an even more direct connection between the bond pads on the chip and the off-chip bonding locations. However, the C4 method, like TAB, has been much more expensive to implement than wirebonding.
In a typical C4 interconnection (also known as flip chip interconnection), the bond pads on an integrated circuit chip are solder bumped. Corresponding solder pads are also formed on the off-chip bonding locations on, for instance, a substrate. The chip solder bumps and substrate solder pads are contacted, then heated to reflow the solder. The solder is then cooled to form a bond between the chip and substrate solder.
Prior to being sold to users, bumped chips for use in C4 interconnection undergo processing that is not necessary for chips that are to be wirebonded. In a typical bumping process, after formation of a passivation layer on the chip surface and formation of vias through the passivation layer to the bond pads, successive layers of chromium, copper and gold are formed over the bond pad. A solder bump is then formed over the chromium, copper and gold layers by evaporating or sputtering solder through a mask. This process is relatively difficult and expensive to perform. As a result, bumped chips for use in a typical C4 interconnection are more expensive to produce and are available from fewer sources than chips for use with wirebonding.